This application claims priority from Korean Patent Application No. 02-47380, filed Aug. 10, 2002, the contents of which are incorporated herein by reference in their entirety.
The present invention relates to integrated circuit devices, and more particularly, to devices including equalization/precharge circuits for complementary data line pairs, such as complementary local and global input/output (I/O) line pairs found in memory circuits.
Dynamic random access memory (DRAM) circuits typically employ shared sense amplifiers to increase density, and include a hierarchical I/O line structure including local I/O line pairs and global I/O line pairs in order to simultaneously access multiple data.
Recently, as operating speeds of DRAMs have increased, signal transmission characteristics of a local I/O line pair and a global I/O line pair have become more critical, particularly signal transmission characteristics of local I/O line pairs. When write and read operations are not being performed, local I/O line pairs typically are equalized and precharged. When a write operation or a read operation is performed, equalization and precharge operations are typically suspended.
In order to improve signal transmission characteristics, the parasitic resistance and capacitance of the complementary lines of a local I/O line pair should be substantially the same. Otherwise, equalization and precharge of the local I/O line pair may occur asymmetrically, which can degrade signal transmission characteristics.
FIG. 1 is a diagram of the layout of a memory cell array portion of a conventional DRAM. Bit line sense amplifier blocks 11a-11d are shared by upper memory cell blocks 13a-13d and lower memory cell blocks 15a-15d. A plurality of left local I/O line pairs LIO0_L/LIO0B_L, LIO1_L/LIO1B_L are connected to the bit line sense amplifier blocks 11a, 11b through a predetermined path (not shown) and are arranged in parallel. A plurality of right local I/O line pairs LIO0_R/LIO0B_R, LIO1_R/LIO1B_R are connected to the bit line sense amplifier blocks 11c, 11d through a predetermined path (not shown) and are arranged in parallel. For convenience of explanation, only two left local I/O line pairs and two right local I/O line pairs are shown in FIG. 1, but it will be appreciated that more I/O line pairs may be present.
The left local I/O line pairs LIO0_L/LIO0B_L, LIO1_L/LIO1B_L are not arranged in pairs. Rather, the left local I/O line pairs LIO0_L/LIO0B_L, LIO1_L/LIO1B_L are arranged in order of a first I/O line LIO0_L, a second I/O line LIO1_L, the complementary line LIO0B_L of the first I/O line and the complementary line LIO01B_L of the second I/O line. Likewise, the right local I/0 line pairs LIO0_R/LIO0B_R, LIO1_R/LIO1B_R are not arranged in units of pair, but are arranged in order of a first I/O line LIO0_R, a second I/O line LIO1_R, the complementary line LIO0B_R of the first I/O line and the complementary line LIO01B_R of the second I/O line. In the regions A, B between respective bit line sense amplifiers are disposed equalization/precharge circuits which equalize and precharge the local I/O line pairs LIO0_L/LIO0B_L, LIO1_L/LIO1B_L, LIO0_R/LIO0B_R, LIO1_R/LIO1B_R.
FIG. 2 is a diagram of the structure of an equalization/precharge circuit in region A of FIG. 1. Two equalization/precharge circuits 21 and 23 are arranged in region A. The equalization/precharge circuit 21 has a first equalization transistor 211, a first precharge transistor 212, a second precharge transistor 213, a second equalization transistor 214, a third precharge transistor 215, and a fourth precharge transistor 216. The equalization/precharge circuit 23 has a first equalization transistor 231, a first precharge transistor 232, a second precharge transistor 233, a second equalization transistor 234, a third precharge transistor 235, and a fourth precharge transistor 236. The first local I/O line pair LIO0, LIO0B is connected to a global I/O line pair GIOi, GIOiB through switch transistors SW1, SW2, and the second local I/O line pair LIO1, LIO1B are connected to a global I/O line pair GIOj, GIOjB.
FIG. 3 is a diagram of the structure of an equalization/precharge circuit in region B of FIG. 2. Two equalization/precharge circuits 31 and 33 are arranged in the region B. The equalization/precharge circuit 31 has a first equalization transistor 311, a second precharge transistor 312, a third precharge transistor 313, a second equalization transistor 314, a third precharge transistor 315, and a fourth precharge transistor 316. The equalization/precharge circuit 33 has a first equalization transistor 331, a second precharge transistor 332, a third precharge transistor 333, a second equalization transistor 334, a third precharge transistor 335, and a fourth precharge transistor 336. The first left local I/O line pair LIO0_L, LIO0B_L is connected to a global I/O line pair GIOm, GIOmB through switch transistors SW5, SW6, and the second right local I/O line pair LIO1_R, LIO1B_R are connected to a global I/O line pair GIOn, GIOnB.
FIG. 4 is a diagram of a conventional layout for the equalization/precharge circuit shown in FIG. 2, and FIG. 5 is a diagram of a conventional layout for the equalization/precharge circuit shown in FIG. 3. FIG. 6 is a diagram of an equivalent circuit that models parasitic resistance and parasitic capacitance in the layout of FIG. 4. EQ1, PCH1, PCH2, EQ2, PCH3, and PCH4 of FIG. 4 correspond to the equalization transistor 231, the precharge transistor 232, the precharge transistor 233, the equalization transistor 214, the precharge transistor 215, and the precharge transistor 216, respectively, of FIG. 2.
In the conventional layouts of FIGS. 4 and 5, an equalization/precharge circuit is arranged below local I/O line pairs LIO0/LIO0B, LIO1/LIO1B. Transistors are connected by using jumped lines, such as bitline poly silicon (bitline poly) or second metal (Metal2), which can make the parasitic resistance and capacitance of the local I/O lines LIO0, LIO1 different from the parasitic resistance and capacitance of the complementary lines LIO0B, LIO1B, as shown in FIG. 6. In particular, the parasitic capacitance CO1 between LIO0 and PCH1 may be different from the parasitic capacitance C01b between LIO0B and PCH2, and the parasitic resistance R01 between LIO0 and PCH1 may be different from the parasitic resistance R01b between LIO0B and PCH2. In addition, the parasitic capacitance C02 between PCH1 and EQ1 may be different from the parasitic capacitance C02b between PCH2 and EQ1, and the parasitic resistance R02 between PCH1 and EQ1 may be different from the parasitic resistance R02b between PCH2 and EQ1. The parasitic capacitance C11 between LIO1 and PCH3 may be different from the parasitic capacitance C11b between LIO1B and PCH4, and the parasitic resistance R11 between LIO1 and PCH3 may be different from the parasitic resistance R11b between LIO1B and PCH4. The parasitic capacitance C12 between PCH3 and EQ2 may be different from the parasitic capacitance C12b between PCH4 and EQ2, and the parasitic resistance R12 between PCH3 and EQ2 may be different from the parasitic resistance R12b between PCH4 and EQ2.
Due to these differences, equalization and precharge operations for the local I/O line LIO0 and its complementary line LIOB may occur asymmetrically, and equalization and precharge operations for the local I/O line LIO1 and its complementary line LIO1B may also occur asymmetrically. Consequently, signal transmission characteristics of the local I/O line pairs may be degraded, which may decrease operating speed.
According to some embodiments of the present invention, an integrated circuit device includes first and second complementary data line pairs, e.g., global or local I/O data line pairs, disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween. The device further includes an equalization transistor including respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair. The device also includes a first precharge transistor including the first source/drain region, a third source/drain region in the substrate displaced from the first source/drain region along the first direction, and a first precharge transistor gate electrode disposed on the substrate between the first and third source/drain regions. A second precharge transistor includes the second source/drain region, a fourth source/drain region in the substrate displaced from the second source/drain region along the first direction, and a second precharge transistor gate electrode disposed on the substrate between the second and fourth source/drain regions. A precharge voltage bus conductor is disposed on the substrate and is electrically coupled to the third and fourth source/drain regions.
The first and second source/drain regions may underlie the first and second data lines of the first complementary data line pair, respectively, and the equalization transistor gate electrode may include a first elongate conductive region disposed between the first and second data lines of the first complementary data line pair. The first and second precharge transistor gate electrodes may include a second elongate conductive region extending along a second direction transverse to the first direction and disposed between the first and third source/drain regions and between the second and fourth source/drain regions. The first elongate conductive region may extend contiguously and substantially perpendicularly from the second elongate conductive region.
According to further embodiments of the invention, the second complementary data line pair includes a second data line disposed adjacent the second data line of the first complementary data line pair, and the device may further include a conductive line disposed adjacent the second data line of the second complementary data line pair and electrically connected to first data line of the first complementary data line pair. A second equalization transistor includes respective fifth and sixth source/drain regions in the substrate that are coupled to respective ones of the second data line of the second complementary data line pair and the conductive line and a second equalization transistor gate electrode disposed on the substrate between the second data line of the second complementary data line pair and the conductive line. A third precharge transistor includes the fifth source/drain region, a seventh source/drain region in the substrate displaced from the fifth source/drain region along the first direction, and a third precharge transistor gate electrode disposed on the substrate between the fifth and seventh source/drain regions. A fourth precharge transistor includes the sixth source/drain region, an eighth source/drain region in the substrate displaced from the sixth source/drain region along the first direction, and a fourth precharge transistor gate electrode disposed on the substrate between the sixth and eighth source/drain regions. The precharge voltage bus conductor is electrically coupled to the seventh and eighth source/drain regions. In some embodiments, the conductive line is coupled to the first data line of the second complementary data line pair by a jumper that crosses the second data line of the first complementary data line pair and the second data line of the second complementary data line pair. In other embodiments, the conductive line includes an extension of the first data line of the second complementary data line pair. The device may further include an equalization transistor including the second and fifth source/drain regions coupled to respective ones of the second data line of the first complementary data line pair and the second data line of the second complementary data line pair and a third equalization transistor gate electrode disposed on the substrate between the second data line of the first complementary data line pair and the second data line of the second complementary data line pair.
According to a further aspect of the present invention, there is provided an equalization/precharge circuit which equalizes and precharges a first data line, a second data line, the complementary data line of the first data line, and the complementary data line of the second data line which are sequentially arranged in parallel to each other and are connected through column selection transistors to a first bit line, a second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line which are connected to a memory cell array, the equalization/precharge circuit including a first equalization transistor which equalizes the first data line and the complementary data line of the first data line; a first precharge transistor which precharges the first data line to a predetermined voltage level; a second precharge transistor which precharges the complementary data line of the first data line to the predetermined voltage level; a second equalization transistor which equalizes the second data line and the complementary data line of the second data line; a third precharge transistor which precharges the second data line to the predetermined voltage level; and a fourth precharge transistor which precharges the complementary data line of the second data line to the predetermined voltage level, wherein the gates of the first equalization transistor, the first precharge transistor, and the second precharge transistor are arranged in an active region being connected to each other in a T shape, and the gates of the second equalization transistor, the third precharge transistor, and the fourth precharge transistor are also arranged in the active region being connected to each other in a T shape.
According to another aspect of the present invention, there is provided an equalization/precharge circuit which equalizes and precharges a first data line, a second data line, the complementary data line of the first data line, and the complementary data line of the second data line which are sequentially arranged in parallel to each other and are connected through column selection transistors to a first bit line, a second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line which are connected to a memory cell array, the equalization/precharge circuit including a first equalization transistor which equalizes the first data line and the complementary data line of the first data line; a first precharge transistor which precharges the first data line to a predetermined voltage level; a second precharge transistor which precharges the complementary data line of the first data line to the predetermined voltage level; a second equalization transistor which equalizes the second data line and the complementary data line of the second data line; a third precharge transistor which precharges the second data line to the predetermined voltage level; a fourth precharge transistor which precharges the complementary data line of the second data line to the predetermined voltage level; and an additional equalization transistor which equalizes the first data line and the second data line, wherein the gates of the first equalization transistor, the first precharge transistor, and the second precharge transistor are arranged in an active region being connected to each other in a T shape, and the gates of the second equalization transistor, the third precharge transistor, and the fourth precharge transistor are also arranged in the active region being connected to each other in a T shape, and the gate of the additional equalization transistor is also arranged in a T shape in the active region.
According to another aspect of the present invention, there is provided a layout structure of an equalization/precharge circuit which equalizes and precharges a first data line, a second data line, the complementary data line of the first data line, and the complementary data line of the second data line which are sequentially arranged in parallel to each other and are connected through column selection transistors to a first bit line, a second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line which are connected to a memory cell array, the layout structure including a first active region; a second active region; and a gate region which is arranged in a T shape in the first active region and is also arranged in a T shape in the second active region, wherein the first active region is separated into three active regions by the T-shape gate region and the three active regions are connected to the first data line, the complementary data line of the first data line, and a predetermined voltage line, respectively, and the second active region is separated into three active regions by the T-shape gate region and the three active regions are connected to the second data line, the complementary data line of the second data line, and the predetermined voltage line, respectively.
It is desirable that the complementary data line of the first data line is connected to one of the three active regions in the first active region through a predetermined jumped pattern line.
It is desirable that the complementary data line of the first data line is connected directly to one of the three active regions in the first active region without a predetermined jumped pattern line.
It is desirable that the first active region and the second active region are one active region in which the two active regions are connected to each other. It is desirable that the first active region and the second active region are connected to each other and on the active region where the two active regions are connected to each other, the gate region is extended and arranged in a T shape.
According to another aspect of the present invention, there is provided a semiconductor memory device including a memory cell array; a first bit line, a second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line which are connected to the memory cell array; a first data line, a second data line, the complementary data line of the first data line, and the complementary data line of the second data line which are sequentially arranged in parallel to each other and are connected through column selection transistors to the first bit line, the second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line; and an equalization/precharge circuit according to an embodiment of the present invention.
According to another aspect of the present invention, there is provided a semiconductor memory device including a memory cell array; a first bit line, a second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line which are connected to the memory cell array; a first data line, a second data line, the complementary data line of the first data line, and the complementary data line of the second data line which are sequentially arranged in parallel to each other and are connected through column selection transistors to the first bit line, the second bit line, the complementary bit line of the first bit line, and the complementary bit line of the second bit line; and an equalization/precharge circuit according to another embodiment of the present invention.
It is desirable that the first and second data lines are local I/O lines or global I/O lines.